Explanation

(c) The circuit diagram of a NAND gate when its two inputs are shorted, is given as
NAND = AND + NOT
The truth table of the logic gate is given as
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[table] $A$ | $Y$ | $\overline{Y}$ ; 0 1 | 0 1 | 1 0 [/table]
Hence, if the input is zero then output is 1 and when input is 1 than output is zero.
So, the resulting gate is NOT gate.