Explanation

(b) The truth table of the circuit is given
[table] $\mathbf{A}$ | $\mathbf{B}$ | $\mathbf{C}$ | $\mathbf{X}\mathbf{=}\overline{\mathbf{AB}}$ | $\mathbf{Y}\mathbf{=}\overline{\mathbf{BC}}$ | $\mathbf{Z}\mathbf{=}\overline{\mathbf{X}\mathbf{+}\mathbf{Y}}$ ; 0 | 0 | 0 | 1 | 1 | 0 ; 1 | 0 | 0 | 1 | 1 | 0 ; 0 | 0 | 1 | 1 | 1 | 0 ; 1 | 0 | 1 | 1 | 1 | 0 ; 0 | 1 | 0 | 1 | 1 | 0 ; 1 | 1 | 0 | 0 | 1 | 0 ; 0 | 1 | 1 | 1 | 0 | 0 ; 1 | 1 | 1 | 0 | 0 | 1 [/table]
Output $Z$ of single three input gate is that of AND gate